ASIC Design Verification Trainings

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ASIC Design Verification Trainings

ASIC Design Verification Fundamentals course is designed to provide participants with a comprehensive understanding of the critical aspects of verifying Application-Specific Integrated Circuits (ASICs). ASICs are integral components of modern electronic systems, and their verification is a crucial step in ensuring their functionality, reliability, and performance.

Product & service Based Companies hiring Trained DV Candidates .

Eligibility Criteria

B.Tech/M/Tech degree in Electronics & Communication (ECE), Electrical & Electronics (EEE), or closely related fields.
B,Tech/M.Tech in Computer Science (CSE) or Closely related Fields
M.Tech in VLSI or closely related fields
While not mandatory, candidates with a basic understanding of digital electronics and proficiency in the C programming language are preferred.

Course Curriculum

Module 1 : Introduction to VLSI

Application of VLSI
Design Process of VLSI
Scope of VLSI
Introduction to VLSI Design flow.

Module 2 : Digital System Design

Number Systems – Review
Logic Minimization
Combinational Circuit Design
Understanding of a Logic Gate
Designing with Mux, Demux, Decoders, Encoders
Sequential Elements – D Latch, D Flop
Design of Sequential Systems – Registers and Counters
Finite State Machine

Module 3 : Introduction to HDL

- History of HDL
- Need and Scope Of HDL
Basic Concepts
- Types of Modeling
- Data Types in Verilog, System Task
- Logic Values
- Port Definition, Declaration
- Port Connection Rule
Gate Level Modeling
- Gate Types
- Gate Delays
- Vectors in Verilog
- Test Bench Basics
- Writing Verilog Modules
- Gate Level Modeling Examples
Dataflow Modeling
- Type of Operators
- Continuous assignment statement
- Regular assignment delay
- Examples Of Data Flow Modeling
Behavioural Modeling
- Initial and Always Statements
- Procedural Assignment Statements
- Timing Control Statements
- If_ else Statements
- Case statement
- Block Statements
- Loops
- Design of Flip-flops
- Design of Digital circuits using Behavioral Modeling
Tasks and Functions
State Machines
- Moore Machines
- Mealy Machines
- Examples of Moore and Mealy Machines
Assignment and Mock Interview

Module 4 : System Verilog Overview

- Overview of System Verilog
- System Verilog Books and Resources
Data Types
- System verilog data types and enumerated types
- Operators
- Queues and Arrays
- Typedefs
- Structures and unions
- Casting
- Packages
- Strings
Flow Control
- Loop enhancements
- Tasks and Functions
- Time values
OOP in System Verilog
- Basics of OOP
- Class Based Randomization
- Advanced OOP
- Class extension & inheritance
- Adding properties & methods to extended classes
- Overriding class methods
- Extending class methods
- Virtual Classes, Methods and Polymorphism
- Dynamic Casting and Parameterized Classes
- Callbacks
Advanced Concepts
- Event scheduling in Verilog 2001
- Event scheduling in System Verilog
Interfaces
- Interface usage overview
- How interfaces work
- Interface constructs
- Interface mod ports
Process Synchronization
- Fork-join processes
- Semaphores
- Events
- Mailboxes
Program Blocks
- Program blocks
- Program block interaction with modules
- Final blocks
- Clocking blocks
- Clocking skews
Functional Coverage
- Types of coverage
- Functional coverage process
- Cover groups and cover points
- Coverage bins
- Cross coverage
System Verilog Assertion
- Assertion based verification
- Assertion types
- Operators
- Property
- Sequence
- Operations
- Binding SVA to Design Blocks
- Assertion directives

Module 5 : Universal Verification Methodology

- - Introduction to UVM
  - Difference between OVM and UVM
  - Coverage-Driven Verification
  - Universal Verification Component (UVC) Structure
  - Transaction level modelling
  - UVM class library
  - UVM features
  Stimulus Modeling
  - Modeling Transactions
  - Field Automation
  - Data Operations (copy, clone, print etc)
  UVM Simulation Phases
  - Standard Phases
  - Run-time Phases
  Creating a Simple Environment
  - UVM Component Classes
  - Structure of a Simple Environment
  - Driver, sequencer, monitor, agent and env
  - Messaging
  Test Classes
  - uvm_test class
  - Test Selection
  Configurations
  - Controlling Environment Behavior
  - Configuring Topology with set_config
  - set_config rules
  - Configuration database
  - Recommendations for set_config and uvm_config_db usage
  - Factories and Creating Data and Objects
  - Type and Instance Overrides
  UVM Sequences
  - Sequence Components
  - uvm_do
  - Alternatives to uvm_do macros
  - Objection mechanism for stopping simulation
  - Sequence libraries
  Configurations
  - The Test bench layer
  - Virtual System Verilog Interfaces
  - Assigning Interfaces using the configuration database
  Multi-Channel Sequences and Scoreboards
  - Interface and Module UVCs
  - Multi-Channel Sequences (Virtual Sequences)
  - Building a Scoreboard
  Transaction Level Modeling (TLM)
  - Concepts and Terminology
  - Simple uni-directional interfaces (put, get, peek)
  - More complex connections (transport, analysis)
  - TLM FIFOs and analysis FIFOs
  - Hierarchical connections with export
  - Analysis
  Register Layer
  - Register layer architecture and features
  - Front door and back door access
  - Mirroring and updating
  - Address maps
  - Register adapters
  - Integrating registers into the environment
  - Register sequences
  - Built-in register test sequences
  Assignment and Mock Interview

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